Tokyo SiTime jobs.contract_type_full_time Regular
About SiTime
SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry.

Job Summary
We at SiTime take pride in being the only company in the market that offers MEMS-based timing solutions. Our MEMS dies are uniquely complemented by our CMOS dies in the same package. We use state of the art analog and digital circuits to achieve very aggressive design specs for our timing solutions. Our precision timing products keep pushing the boundaries of the industry across all dimensions and are by far superior to our competition. This has enabled us to continuously gain market share.

Responsibilities:

  • Develop micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)

  • Develop the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL

  • Develop standalone testbenches to verify the RTL behavior

  • Write and verify SystemVerilog Assertions (SVA) for a design

  • Write timing constraints and clock definition for synthesis and place and route tools

  • Run industry-standard synthesis tools (e.g., Genus or Design Compiler) and be able to fix the timing problems if they arise

  • Understand various design tradeoffs including timing/area/power and know how to improve them

  • Read and understand the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time)

  • Cross functional interactions and communication with various teams within SiTime including analog, verification, backend, system and test engineering teams

  • Post-Si bring-up, validation and debugging



Qualifications & Requirements (Education must be included):

  • Master's degree in electrical engineering plus 5 years of relevant work experience in the industry

  • Excellent verbal and written communication skills in English

  • Proficient in Verilog and SystemVerilog

  • Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc

  • Experience in designing mixed-signal digital logic

  • Basic understanding of Discrete time Signal Processing theory, FIR and IIR filter design

  • Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA

  • Skilled in scripting languages Perl/Tcl/Python



Desired Characteristics & Attributes:

  • PhD in electrical/computer engineering plus 3 years of relevant industry experience

  • 2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing

  • 2-5 years of experience in designing Digital Phase-Locked Loops (DPLL)

  • Experience in complex FSM design

  • Familiarity with MATLAB, Simulink or any other high-level modeling tools

  • Experience in low-power digital design flow

  • Basic understanding of the Control Theory



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