Description
Responsibilities:
- Support and enhance EDA flow for full-cycle chip design in both Analog and Digital
- Collaborate with global CAD teams on unified design flow automation
- Promote and support unified EDA flow for design teams
- Work closely with product developers in solving CAD related issues and developing enhancements to make CAD tools more productive and easier to use
- BSEE and 8+ years of relevant experience on RTL2GDS design flow development
- Hands-on experience in Virtuoso platform, Calibre and timing closure.
- Must have efficient scripting experience in one of more of the following: Perl, Python, or TCL, C++, or Makefile.
- Experience in supporting EDA flow for different design teams
- People management experience is a plus
- Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English and Japanese
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