Onomichi TSMC
Key Areas of Responsibility

Analog PLL / All digital PLL design at TSMC advance process node
Mixed mode design flow at advanced process.
Device benchmark from PLL circuit point of view

Requirements


Qualifications:
Minimum of master degree majoring in EE. Higher degree is preferred.
Familiar with basic PLL theory and using Matlab codes to model PLL.
Familiar with Spread-Spectrum-Clocks.
Have designed (analog, or all-digital) PLLs

The Following Are Preferred But Not Required

Have done measurements, and/or designs of PCBs.
Design experiences in phase-noise BIST circuits
Experiences in PLL layout constraints and floor-planning
Experiences above 10GHz LC-tank PLLs
Digital design experiences (Verilog & APR)

Languages:
Capable of very effective communications in oral and written English

Key Experience

Preferable with above 5 years of working experience.
Additional experience in device/integration/product engineering would be advantageous.

Personal Attributes

Proactive and willing to take challenges.
Highly self-motivated to learn new things and build new skills
Strong in project management, communication, and organizing information


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

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