Onomichi Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

システム・機能検証 担当アプリケーション・エンジニア

応募資格
大卒 (電気・電子、コンピュータサイエンス)、またはそれに準じる経験、
知識をお持ちの方で新しいことに意欲的にチャレンジ出来る方
経験/スキル
6年以上のHDL設計・検証の業務経験を持つ方
EDAツール(主に機能シュミレータ、デバッガ)の利用経験がある方
EDA ツール自体の評価などの経験がある方
ハードウェアエミュレータやFPGAを使用した製品開発の経験がある方であればお尚よし
業務を効率良く行うためのプログラミング・スキルを持つ方(シェル、C/C++, Perl、Tcl、Python、Ruby等の活用経験)
検証言語(HDL/SystemVerilog/e/SystemC)や検証メソドロジ(UVM等)に
よる検証環境構築もしくは機能検証の経験がある方
顧客が抱える検証課題に対して最適なソリューションを提供する事ができ、
顧客と良好な信頼関係を継続して構築できる方
日本語・英語でのメールのやり取り及び技術的会話に支障がない事
問題解決能力があり、モチベーションを高く持って自ら業務を進められる方
自らの活動範囲に制限を設けず、何事にも貪欲に取り組み、新しい技術を吸収しながら成長していける方
業務内容
ケイデンスの機能検証製品に関する顧客向け技術プリセールス、及び、ポストサポート業務

Application Engineer – Functional Verification
Qualification Requirements
Bachelor's degree in Computer Science, Electrical/Electronic Engineering, or related field
Has the knowledge and desire to take on new challenges
Experiences/Skills
At least 6 years' experience in HDL design and verification
Experience in using EDA tools (mainly functional simulators and debuggers)
Experience in evaluating EDA tools
Experience in product development using hardware emulators and FPGAs is plus.
Programming skills to efficiently perform tasks (practical experience in shell scripting, C/C++, Perl, Tcl, Python, Ruby, etc.)
Experience in construction of verification environments or functional verification using verification languages(HDL/SystemVerilog/e/SystemC) or verification methodologies (UVM, etc.)
Can provide optimal solutions to the verification tasks that customers have and can continue to build good trust with customers
Can communicate in both Japanese and English (email exchange and technical discussion)
Ability to solve problems; can work independently with high motivation
Does not put restrictions on scope of work, engages in everything with a passion, and can grow while absorbing new technologies
Job Description
Technical pre-sales and post-sales services for customers of Cadence's functional verification products

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