Yokohama ReachExt K.K.

Seeking a highly skilled Design Verification Engineer with 8+ years of experience.

  • Expertise in RTL design using Verilog HDL and EDA verification with NC Verilog.
  • Proficient in Microsoft Office software, including Excel, Word, and Outlook.
  • Familiarity with Linux CUI commands and version control tools, such as Subversion and git.
  • Experience with SystemVerilog Assertions (SVA) and UVM.

Key Responsibilities:

  • Under general supervision, perform engineering work and applied research to develop new Integrated Chips.
  • Contribute to architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging of Chips.

Language Requirement:

Bilingual English and Japanese proficiency at N2 level or above is required.

Estimated salary: $120,000 - $180,000 per year.



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